FPGA Based S/PDIF Input DAC

I am in the process of creating a Delta Sigma (ΔΣ) Digital to Analogue Converter in the audio range using a Spartan 3E 500k on a Papilio One development board with a S/PDIF (Sony Phillips Digital Interconnect Format) receiver.

It will be a multi staged, modular design.  On a system level it will involve the analogue signal conditioning from a coaxial cable to 3.3V digital levels, signal decoding from the S/PDIF protocol, multi-order Sigma Delta DAC and finally an analogue reconstruction filter.  Suffice to say it will be a multi-faceted project and at all times I will be aiming for the best possible quality as the ultimate aim is for this to be my main DAC for my KRK Rokit 5 studio monitors.

By and large I will discuss the process of the design of this device as I create it and that will be in the same order as the signal chain, ie. the order described above.  I will provide as much quantifiable data as possible and will certainly be voicing my opinions on better ways to achieve things, if only for my own reference.